Semiconductor integrated circuits employing field-effect elements as the fundamental constituents have rapidly progressed in the aspects of integration scale and circuit performance owing to the development of the FET fabricating technique of the self-alignment type which uses, e.g., polycrystalline silicon for a gate electrode. In recent years, the technique of an integrated circuit having a two-level gate electrode in which a second gate electrode is placed over a first gate electrode has been developed, thereby further accelerating the degree of progress. By way of example, it is now possible to integrate a random access memory (RAM) of 16 K bits on a single silicon semiconductor wafer.
An example of the structure of such a memory is described in, "The Hi-C RAM Cell Concept" by A. F. Tasch, Jr., P. K. Chatterjee, H-S, Fu, and T. C. Halloway, published in Technical Digest of International Electron Devices Meeting in 1977, pp. 287-290. In the memory having the multi-level gate electrodes, inter-layer insulating layers are provided between the first and second gate electrodes and on the respective gate electrodes. Further, the respective openings are formed in the insulating layers on the respective gate electrodes, in which openings interconnection conductors are disposed so as to be connected with the gate electrodes. According to the prior art, these openings are simultaneously provided by etching, where the thicknesses of the insulating layers to be etched and removed are different for the respective openings. Accordingly, the openings formed have different sizes, with some openings being too large while other openings are too small. Moreover, it is difficult to control making the openings to be predetermined sizes. With the prior art, therefore, the fabrication is difficult. When it is intended to avoid such problems, the density of integration lowers.
The above problems apply, not only to a semiconductor device having FET elements of a multi-level gate structure, but also generally to a semiconductor device which has a plurality of semiconductor circuit elements in or on a semiconductor substrate and in which at least parts of electrodes of the respective circuit elements have a multi-level structure, as well as to a process for making the same.